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VPX-D16A4-SRIO

VPX-D16A4-SRIO

简介: SRIO 接口 VPX信号处理卡
数据表: http://www.commagility.com/images/pdfs/datasheets/CA-VPX-D16A4-SRIO.pdf
产品详情

The VPX-D16A4-SRIO is a rugged high performance DSP/FPGA card in the compact VITA 65, 3U OpenVPX form factor. It is ideal for applications such as EW, SW radio, imaging or radar in harsh field deployment environments.

The card features 4x ARM A15 cores, 16x C66x+ DSP cores and various accelerators across two TI Keystone SoCs, each with its own large DDR3 memory bank and a 20Gbaud SRIO link to the VPX backplane. They are closely coupled with the Hyper-Link bus. The main DSP is connected via PCI Express and AIF2 CPRI interfaces to a Xilinx Kintex-7 K325T FPGA, which has its own backplane MGT, LDVS, GPIO and seri-al ports and a flexible clock generation PLL, enabling specialised I/O such as multi-channel RF or high speed ADC/DAC interfaces. All devices are also connected with Gigabit Ethernet.

A full Linux BSP and example software support is provided to accelerate customer development, based on TI’s Linux and Multicore Software Development Kit and the Xilinx Vivado FPGA development suite. In addition, CommAgility’s field proven LTE PHY software is available integrated with the card, with various options for L2/L3 software stacks.

Key Features

Form Factor:  

  3U OpenVPX card conforming to  AV65-2010, 1” pitch and a payload  profile of MOD3-PAY-2F2U-16.2.3-8

  Rugged conduction or air cooled

  Universal keying (unkeyed)

DSP0: Texas Instruments TCI6636/38 or 66AK2H12/14 KeystoneII DSP/ARM SoC

  4 x 1.4 GHz ARM A15 cores

  8 x 1.2 GHz C66x DSP cores

  Wireless accelerators (TCI parts only)

  2 Gbytes x64 DDR3-1600 SDRAM

  256 Mbytes x16 boot FLASH

  GigE to FPGA0, DSP1 and backplane

  HyperLink to DSP1 at up to 50 Gbaud

  2x 5Gbaud PCIe to FPGA

  2x AIF2 to FPGA

  4x 5Gbaud SRIO to backplane

  10 GigE XFI to backplane

(TCI6638/66AK2H14 only)

 

DSP1: Texas Instruments TMS320C6678  Keystone DSP SoC

  8 x 1.25GHz C66x DSP cores

  2 Gbytes x64 DDR3-1333 SDRAM

  GigE and HyperLink to DSP0

  4x 5Gbaud SRIO to backplane

FPGA: Xilinx Kintex-7 K325T

  FFG676 package allows K160T to K410T

  1 Gbyte x32 DDR3-1600 SDRAM

  256 Mbytes x16 FLASH; allows storage of multiple FPGA configuration images  

  3x MGT, 32x LVDS, UART to backplane

  GigE to DSP0