The VPX571 provides dual integrated RF transceivers, each based on AD9364. One channel includes a programmable filter on transmit. The module is compatible with Analog Devices RadioVerse design tools.
The Module routes its RF as an option to the VITA 67.2 connector or to the front panel. The module has 8 TX/RX SERDES, Dual GbE, 8 LVDS (could be configured as singled ended), CPU RS-232 and management RS-232 to the P1 connector.
The FPGA has interface to a single DDR4 memory channel (64-bit wide). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.
The module is based on Xilinx UltraScale+ XCZU15EG MPSoC FPGA, which has 3528 DSP Slices and 746k logic cells. The XCZU15EG includes quad-core ARM application processor, dual-core ARM real-time processor and Mali™ graphics processing unit, as well as over 26 Mb of block RAM and 31 Mb of UltraRAM.
The module has on board 64 GB of Flash, 128 MB of Boot Flash and an SD Card as an option.
Key Features
Dual RF transceiver, AD9364
Xilinx UltraScale+ XCZU15EG FPGA
8 GB of 64-bit wide DDR-4 Memory (single bank) with ECC
MPSoC with block RAM and UltraRAM
RF routed as option to VITA 67.2
Health Management through dedicated Processor
